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AND Gate

September 04, 2021
and_gate_schematic.png

Description

This is the schematic of an AND Gate, which has been implemented in VHDL, and the FPGA design was transferred onto the Nexus A7-T100 board.  Testbench results are below.

and_gate_waveform.png

Input A is running on a manual forced clock turning ON/OFF every 300 ns, and Input B is running on manual forced clock turning ON/OFF every 100 ns.  The output Y is reflected in schematic.

Test Bench

Industry Noor

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